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PRELIMINARY INFORMATION
ICS270
Triple PLL Field Programmable VCXO Clock Synthesizer
Description
The ICS270 field programmable VCXO clock synthesizer generates up to eight high-quality, high-frequency clock outputs including multiple reference clocks from a low-frequency crystal input. It is designed to replace crystals and crystal oscillators in most electronic systems. Using ICS' VersaClockTM software to configure PLLs and outputs, the ICS270 contains a One-Time Programmable (OTP) ROM for field programmability. Programming features include VCXO, eight selectable configuration registers and up to two sets of four low-skew outputs. Using Phase-Locked Loop (PLL) techniques, the device runs from a standard fundamental mode, inexpensive crystal, or clock. It can replace VCXOs, multiple crystals and oscillators, saving board space and cost. The ICS270 is also available in factory programmed custom versions for high-volume applications.
Features
* * * * * * * * * * *
Packaged as 20-pin TSSOP Eight addressable registers Replaces multiple crystals and oscillators Output frequencies up to 200 MHz at 3.3 V Input crystal frequency of 5 to 27 MHz Up to eight reference outputs Up to two sets of four low-skew outputs Operating voltages of 3.3 V Controllable output drive levels Advanced, low-power CMOS process Available in Pb (lead) free packaging
Block Diagram
VDD 3
S2:S0
3
OTP ROM with PLL Values
CLK1 PLL1 CLK2 Divide Logic and Output Enable Control CLK3 CLK4 CLK5 CLK6 CLK7 CLK8
PLL2
VIN PLL3 X1 Crystal X2 External capacitors are required. Voltage Controlled Crystal Oscillator GND 2
PDTS
MDS 270 B Integrated Circuit Systems, Inc.
1
525 Race Street, San Jose, CA 95126
Revision 040705 tel (408) 297-1201
www.icst.com
PRELIMINARY INFORMATION
ICS270 Triple PLL Field Programmable VCXO Clock
Pin Assignment
VIN S0 S1 VDD CLK1 CLK2 CLK3 CLK4 GND X1 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 S2 VDD PDTS GND CLK8 CLK7 CLK6 CLK5 VDD X2
20 pin (173 mil) TSSOP
Pin Descriptions
Pin Number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Pin Name
VIN S0 S1 VDD CLK1 CLK2 CLK3 CLK4 GND X1 X2 VDD CLK5 CLK6 CLK7 CLK8 GND PDTS VDD S2
Pin Type
Input Input Input Power Output Output Output Output Power XI XO Power Output Output Output Output Power Input Power Input
Pin Description
Voltage input to VCXO. Zero to 3.3 V signal which controls the VCXO frequency Select pin 0. Internal pull-up resistor. Select pin 1. Internal pull-up resistor. Connect to +3.3 V. Output clock 1. Weak internal pull-down when tri-state. Output clock 2. Weak internal pull-down when tri-state. Output clock 3. Weak internal pull-down when tri-state. Output clock 4. Weak internal pull-down when tri-state. Connect to ground. Crystal input. Connect this pin to a crystal. Crystal Output. Connect this pin to a crystal. Connect to +3.3 V. Output clock 5. Weak internal pull-down when tri-state. Output clock 6. Weak internal pull-down when tri-state. Output clock 7. Weak internal pull-down when tri-state. Output clock 8. Weak internal pull-down when tri-state. Connect to ground. Power-down tri-state. Powers down entire chip and tri-states clock outputs when low. Internal pull-up resistor. Connect to +3.3 V. Select pin 2. Internal pull-up resistor.
MDS 270 B Integrated Circuit Systems, Inc.
2
525 Race Street, San Jose, CA 95126
Revision 040705 tel (408) 297-1201
www.icst.com
PRELIMINARY INFORMATION
ICS270 Triple PLL Field Programmable VCXO Clock
External Components
The ICS270 requires a minimum number of external components for proper operation. The external crystal must be connected as close to the chip as possible and should be on the same side of the PCB as the ICS270. There should be no via's between the crystal pins and the X1 and X2 device pins. There should be no signal traces underneath or close to the crystal. See application note MAN05.
Series Termination Resistor
Clock output traces over one inch should use series termination. To series terminate a 50 trace (a commonly used trace impedance), place a 33 resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20.
Crystal Tuning Load Capacitors
The crystal traces should include pads for small fixed capacitors, one between X1 and ground, and another between X2 and ground. Stuffing of these capacitors on the PCB is optional. The need for these capacitors is determined at system prototype evaluation, and is influenced by the particular crystal used (manufacture and frequency) and by PCB layout. The typical required capacitor value is 1 to 4 pF. To determine the need for and value of the crystal adjustment capacitors, you will need a PC board of your final layout, a frequency counter capable of about 1 ppm resolution and accuracy, two power supplies, and some samples of the crystals which you plan to use in production, along with measured initial accuracy for each crystal at the specified crystal load capacitance, CL. To determine the value of the crystal capacitors: 1. Connect VDD of the ICS270 to 3.3 V. Connect pin 1 of the ICS270 to the second power supply. Adjust the voltage on pin 1 to 0V. Measure and record the frequency of the CLK output. 2. Adjust the voltage on pin 1 to 3.3 V. Measure and record the frequency of the same output. To calculate the centering error:
Decoupling Capacitors
As with any high-performance mixed-signal IC, the ICS270 must be isolated from system power supply noise to perform optimally. Decoupling capacitors of 0.01F must be connected between each VDD and the PCB ground plane. For optimum device performance, the decoupling capacitor should be mounted on the component side of the PCB. Avoid the use of vias on the decoupling circuit.
Quartz Crystal
The ICS270 VCXO function consists of the external crystal and the integrated VCXO oscillator circuit. To assure the best system performance (frequency pull range) and reliability, a crystal device with the recommended parameters (shown below) must be used, and the layout guidelines discussed in the following section shown must be followed. The frequency of oscillation of a quartz crystal is determined by its "cut" and by the load capacitors connected to it. The ICS270 incorporates on-chip variable load capacitors that "pull" (change) the frequency of the crystal. The crystal specified for use with the ICS270 is designed to have zero frequency error when the total of on-chip + stray capacitance is 14 pF. Recommended Crystal Parameters: Initial Accuracy at 25C Temperature Stability Aging Load Capacitance Shunt Capacitance, C0 C0/C1 Ratio Equivalent Series Resistance
6 ( f3.0V - ft arg et ) + ( f0V - ft arg et ) Error = 10 x ---------------------------------------------------------------------- - errorxtal ft arg et
20 ppm 30 ppm 20 ppm 14 pf 7 pF Max 250 Max 35 Max
Where: ftarget = nominal crystal frequency
MDS 270 B Integrated Circuit Systems, Inc.
3
525 Race Street, San Jose, CA 95126
Revision 040705 tel (408) 297-1201
www.icst.com
PRELIMINARY INFORMATION
ICS270 Triple PLL Field Programmable VCXO Clock
errorxtal =actual initial accuracy (in ppm) of the crystal being measured If the centering error is less than 25 ppm, no adjustment is needed. If the centering error is more than 25ppm negative, the PC board has excessive stray capacitance and a new PCB layout should be considered to reduce stray capacitance. (Alternately, the crystal may be re-specified to a higher load capacitance. Contact ICS for details.) If the centering error is more than 25 ppm positive, add identical fixed centering capacitors from each crystal pin to ground. The value for each of these caps (in pF) is given by: External Capacitor = 2 x (centering error)/(trim sensitivity) Trim sensitivity is a parameter which can be supplied by your crystal vendor. If you do not know the value, assume it is 30 ppm/pF. After any changes, repeat the measurement to verify that the remaining error is acceptably low (typically less than 25 ppm).
banks to support widely differing frequency values from the same PLL. Each output frequency can be represented as:
OutputFreq ---M N
=
REFFreq
Output Drive Control
The ICS270 has two output drive settings. Low drive should be selected when outputs are less than 100 MHz. High drive should be selected when outputs are greater than 100 MHz. (Consult the AC Electrical Characteristics for output rise and fall times for each drive option.)
ICS VersaClock Software
ICS applies years of PLL optimization experience into a user friendly software that accepts the user's target reference clock and output frequencies and generates the lowest jitter, lowest power configuration, with only a press of a button. The user does not need to have prior PLL experience or determine the optimal VCO frequency to support multiple output frequencies. VersaClock software quickly evaluates accessible VCO frequencies with available output divide values and provides an easy to understand, bar code rating for the target output frequencies. The user may evaluate output accuracy, performance trade-off scenarios in seconds.
ICS270 Configuration Capabilities
The architecture of the ICS270 allows the user to easily configure the device to a wide range of output frequencies, for a given input reference frequency. The frequency multiplier PLL provides a high degree of precision. The M/N values (the multiplier/divide values available to generate the target VCO frequency) can be set within the range of M = 1 to 1024 and N = 1 to 32,895. The ICS270 also provides separate output divide values, from 2 through 63, to allow the two output clock
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS270. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.
Parameter
Supply Voltage, VDD Inputs Clock Outputs
Condition
Referenced to GND Referenced to GND Referenced to GND
Min.
-0.5 -0.5
Typ.
Max.
7 VDD+0.5 VDD+0.5
Units
V V V
MDS 270 B Integrated Circuit Systems, Inc.
4
525 Race Street, San Jose, CA 95126
Revision 040705 tel (408) 297-1201
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PRELIMINARY INFORMATION
ICS270 Triple PLL Field Programmable VCXO Clock
Parameter
Storage Temperature Soldering Temperature Junction Temperature
Condition
Max 10 seconds
Min.
-65
Typ.
Max.
150 260 125
Units
C C C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature (ICS270PG/PGLF) Ambient Operating Temperature (ICS270PGI/PGILF) Power Supply Voltage (measured in respect to GND) Power Supply Ramp Time Reference crystal parameters
Min.
0 -40 +3.135
Typ.
Max.
+70 +85
Units
C C V ms
+3.3
+3.465 4
Refer to page 3
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature -40 to +85C
Parameter
Operating Voltage
Symbol
VDD
Conditions
Config. Dependent - See VersaClockTM Estimates
Min.
3.135
Typ.
Max.
3.465
Units
V mA
Operating Supply Current Input High Voltage Input High Voltage Input Low Voltage Input High Voltage, PDTS Input Low Voltage, PDTS Input High Voltage Input Low Voltage Output High Voltage (CMOS High) Output High Voltage Output Low Voltage Short Circuit Current Nom. Output Impedance
IDD
Eight 33.3333 MHz outs, PDTS = 1, no load, Note 1 PDTS = 0, no load, Note 1 S2:S0 S2:S0 VDD-0.5 VDD/2+1
27 500 0.4 0.4
mA A V V V V V VDD/2-1 V V V 0.4 V
VIH VIL VIH VIL VIH VIL VOH VOH VOL IOS ZO
ICLK ICLK IOH = -4 mA IOH = -8 mA (Low Drive); IOH = -12 mA (High Drive) IOL = 8 mA (Low Drive); IOL = 12 mA (High Drive) Low Drive High Drive
VDD/2+1 VDD-0.4 2.4
40 70 20 mA
MDS 270 B Integrated Circuit Systems, Inc.
5
525 Race Street, San Jose, CA 95126
Revision 040705 tel (408) 297-1201
www.icst.com
PRELIMINARY INFORMATION
ICS270 Triple PLL Field Programmable VCXO Clock
Parameter
Internal Pull-up Resistor Internal Pull-down Resistor Input Capacitance
Symbol
RPUS RPD CIN
Conditions
S2:S0, PDTS CLK outputs Inputs
Min.
Typ.
190 220 4
Max.
Units
k k pF
Note 1: Example with 25 MHz crystal input with eight outputs of 33.3 MHz, no load, and VDD = 3.3 V.
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature -40 to +85 C
Parameter
Input Frequency Output Frequency Crystal Pullability VCXO Gain Output Rise/Fall Time Output Rise/Fall Time Duty Cycle Power-up time
Symbol
FIN FP
Conditions
Fundamental crystal 0V< VIN < 3.3 V, Note 1 VIN = VDD/2 + 1 V, Note 1
Min.
5 0.314 100
Typ.
Max. Units
27 200 MHz MHz ppm ppm/V ns ns 60 10 2 % ms ms ps ps 250 ps
110 1.0 2.0 40 49-51 4 0.6 50 +200 -250
tOF tOF
80% to 20%, high drive, Note 2 80% to 20%, low drive, Note 2 Note 3 PLL lock-time from power-up PDTS goes high until stable CLK output
One Sigma Clock Period Jitter Maximum Absolute Jitter Pin-to-Pin Skew tja
Configuration Dependent Deviation from Mean, Configuration Dependent Low Skew Outputs
Note 1: External crystal device must conform with Pullable Crystal Specifications listed on page 3. Note 2: Measured with 15 pF load. Note 3: Duty Cycle is configuration dependent. Most configurations are min 45% / max 55%.
Thermal Characteristics
Parameter
Thermal Resistance Junction to Ambient
Symbol
JA JA JA JC
Conditions
Still air 1 m/s air flow 3 m/s air flow
Min.
Typ.
93 78 65 20
Max. Units
C/W C/W C/W C/W
Thermal Resistance Junction to Case
MDS 270 B Integrated Circuit Systems, Inc.
6
525 Race Street, San Jose, CA 95126
Revision 040705 tel (408) 297-1201
www.icst.com
PRELIMINARY INFORMATION
ICS270 Triple PLL Field Programmable VCXO Clock
Marking Diagrams
20 11
Marking Diagrams (Pb free)
20 11
270PG ###### YYWW
1 20 10 11
270PGL ###### YYWW
1 20 10 11
270PGI ###### YYWW
1 10
270PGIL ###### YYWW
1 10
Notes: 1. ###### is the lot number. 2. YYWW is the last two digits of the year and week that the part was assembled. 3. "I" denotes industrial temperature range (if applicable). 4. "L" denotes Pb (lead) free package. 5. Bottom marking: country of origin.
MDS 270 B Integrated Circuit Systems, Inc.
7
525 Race Street, San Jose, CA 95126
Revision 040705 tel (408) 297-1201
www.icst.com
PRELIMINARY INFORMATION
ICS270 Triple PLL Field Programmable VCXO Clock
Package Outline and Package Dimensions (20-pin TSSOP, 173 Mil. Body)
Package dimensions are kept current with JEDEC Publication No. 95
24
Millimeters Symbol
E1 E
Inches Min Max
Min
Max
INDEX AREA
12 D
A A1 A2 b C D E E1 e L
-- 1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 6.40 6.60 6.40 BASIC 4.30 4.50 0.65 Basic 0.45 0.75 0 8
-- .047 0.002 0.006 0.032 0.041 0.007 0.012 0.0035 0.008 0.252 0.260 0.252 BASIC 0.169 0.177 0.0256 Basic .018 .030 0 8
A2 A1
A c
- Ce
b SEATING PLANE
.10 (.004)
C
L
Ordering Information
Part / Order Number
ICS270PG ICS270PGI ICS270PGLF ICS270PGILF See page 7
Marking
Shipping Packaging
Tubes Tubes Tubes Tubes
Package
20-pin TSSOP 20-pin TSSOP 20-pin TSSOP 20-pin TSSOP
Temperature
0 to +70C -40 to +85C 0 to +70C -40 to +85C
Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. VersaClockTM is a trademark of Integrated Circuit Systems, Inc. All rights reserved.
MDS 270 B Integrated Circuit Systems, Inc.
8
525 Race Street, San Jose, CA 95126
Revision 040705 tel (408) 297-1201
www.icst.com

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